1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor in which a metal oxide semiconductor (MOS) transistor having a relatively thick gate insulating film and a MOS transistor having a relatively thin gate insulating film are formed simultaneously.
2. Description of the Related Art
In recent years, a large variety of mobile devices have been widely distributed, and lithium ion batteries, which have high energy density and no memory effect, are widely used as a power source for them. Accordingly, there is also a demand for protection ICs for detecting overcharging and over-discharging of the lithium ion batteries. For example, in the lithium ion batteries of mobile phones, a battery voltage is about 3.6 V. However, a voltage equal to or higher than 20 V is applied during charging, and hence the ICs are required to include elements having high withstanding voltage.
In this case, when the above-mentioned IC specification is supposed to be satisfied through a CMOS transistor manufacturing process, a MOS transistor suitable for a low withstanding voltage and a MOS transistor suitable for a high withstanding voltage should be formed. The reason is as follows. The size of a high withstanding voltage element needs to be formed relatively large so as to satisfy the specification, and when the entire IC is formed using only the high withstanding voltage elements, the final chip size increases, making the IC weak in cost competitiveness, and making it difficult to satisfy demands for price from the market. Accordingly, the chip size should be suppressed by using high withstanding voltage elements in a circuit portion to which high voltage is applied and by using low withstanding voltage elements in other circuit regions.
For the reason described above, a semiconductor device in which gate oxide films are formed to have different thicknesses appropriate for obtaining high withstanding voltage and low withstanding voltage, respectively, and a manufacturing method therefor are essential.
Hereinafter, a conventional manufacturing method for a semiconductor device having gate oxide films of different thicknesses is described. FIGS. 4A to 4E illustrate steps of a manufacturing flow of the conventional semiconductor device. First, as illustrated in FIG. 4A, field insulating films 23 are formed on a semiconductor substrate 52 in an element separation region by a so-called LOCOS method. Under the field insulating films 23, inversion-preventing diffusion layers 31 are formed. The diffusion layers are formed by, for example, an ion implantation method, using a nitride film deposited for formation of the field insulating films 23 as a mask.
Next, as illustrated in FIG. 4B, a first gate insulating film 24 being relatively thick is formed by thermal oxidation. After that, as illustrated in FIG. 4C, a photo resist 41 is formed in a region where a high withstanding voltage element is formed by a photolithography method. Then, using the photo resist 41 as a mask, the first gate insulating film 24 in a region where a low withstanding voltage element is formed is etched to be removed.
Next, a second gate oxide film 25 being relatively thin is formed by thermal oxidation, to thereby obtain a structure illustrated in FIG. 4D. Then, as illustrated in FIG. 4E, gate electrodes 51 are formed of, for example, a polycrystalline silicon film. In this manner, it is possible to obtain a MOS structure having different gate oxide film thickness on the semiconductor substrate 52 (for example, see JP 58-100450 A, JP 01-110761 A, and JP 03-231456 A).
In the conventional manufacturing method for a semiconductor device as described above, the first gate insulating film 24 should be unfailingly removed in the region where the low withstanding voltage element is formed. Further, considering the process fluctuation of the thickness of the first gate insulating film 24, over etching should be performed. In this case, in the region where the low withstanding voltage element is formed, a thinning region of the field insulating film 23 formed by the LOCOS method, that is, a region called “bird's beak”, may also be etched, resulting in exposure of the surface of the semiconductor substrate 52 with a hollow.
As a result, the size of the region where the low withstanding voltage element is formed varies depending on the bird's beak length of the field insulating film 23 and the etching fluctuation of the first gate oxide film 24. In other words, a width of the MOS transistor easily varies, and hence fluctuation of the characteristic of the MOS transistor is easily generated in this structure. Further, as a result, the inversion-preventing diffusion layer 31 formed under the field insulating film 23 comes into existence in the region where the low withstanding voltage element is formed. Due to influences of the above, a so-called narrow-channel effect, in which a threshold voltage undesirably increases when a channel width of the MOS transistor is designed to be short, easily appears. Further, since the degree of the narrow-channel effect significantly varies due to fluctuation of the channel width, the MOS transistor might be manufactured by a manufacturing method with low controllability.
Further, a crystal structure of the semiconductor substrate surface at the bird's beak portion, where the first gate insulating film 24 is etched, is considered to be distorted due to a stress generated by the presence of nitride film during the formation of the field insulating film by the LOCOS method. Then there is a possibility that the second gate insulating film 25 having low quality is formed, and there remains concern for reliability of the gate insulating film.
As described above, in the conventional manufacturing method for a semiconductor device, there is a problem in that the element size is required to be set large so as to reduce the element characteristic fluctuations, which unfavorably leads to increase in chip size. Further, there is a problem in that a fear in terms of gate insulating film reliability still remains even if the element size is increased.